The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of improving memory subsystem performance.
Memory subsystems are an important part of today""s digital electronic systems, including computer systems. Computer system processors are typically coupled to system memory via a memory controller. Other system components may also access the system memory via the memory controller.
The memory controller communicates with the system memory by way of a variety of signals. At least one clock signal is typically coupled between the memory controller and the system memory. A number of command signals are also coupled between the memory controller and the system memory. Further, a number of address lines and data lines are coupled between the memory controller and the system memory.
The system memory may physically reside on one or more memory modules where each module includes a number of memory devices. The system memory may be logically organized into banks. The system memory may be implemented using synchronous dynamic random access memory (SDRAM) devices.
FIG. 1 is a timing diagram of a typical series of read transactions from system memory. At time T1, the memory controller delivers an activate command (ACT) for a first bank (b1). The activate command is accompanied by a row address (ROWa) on the address lines. At time T3, a read command (READ b1) for the first bank is issued accompanied by a column address (COLa) on the address lines. The data (D0-D3) for this read transaction is returned from the system memory beginning at time T6.
At time T4 the memory controller begins another read transaction by issuing another activate command (ACT) for a second bank (b2) accompanied by a row address (ROWb). The read command (READ b2) for the second bank is issued at time T6 along with a column address (COLb). The data (D0-D3) for this read transaction is returned from the system memory beginning at time T9.
Also at time T9, a precharge command (PRE b1) is issued for the first bank. At time T10, another read command (READ b2) for the second bank is issued along with a column address (COLc). The data (D0-D3) for this read command is returned beginning at time T13.
An activate command (ACT b1) for the first bank follows two clock periods (at time T11) after the precharge command issued at time T9. The activate command is accompanied by a row address (ROWc). Two clock periods following the activate command, a read command (READ b1) is issued for the first bank accompanied by a column address (COLd).
As can be seen by looking at the command stream of FIG. 1, the command signals are very active. It would be desirable to make more efficient use of the command bus and to simplify memory controller command scheduler design.